Recommended for reading

• Automated macro-model extraction using spice netlist
• This paper discusses the techiniques to automatically extract the design in formats like CPF, UPF etc so as to verfiy the correctness of the digital models assumed in the SoC implementatoin flow.

• Challenges in hierarchical timing closure using various timing models
• The challenges involved in using various timing models for timing closure and physical implementation are discussed in this paper.

• Modeling non-linearity in Timing analysis
• There are various non-linearities involved in the behaviour of digital circuits in SoC design. Efficient modeling of these non-linearities in a linear and calculation efficient model is discussed in this paper.
• Timing friendly clock gating/divider cell for waveform shaping
• Design of a multi-functional cell for using any of the 50 % divided/gated/bypassed/puch-through clock is discussed in this paper.

• Enhanced timing closure using latches 
• This paper discusses how we can utilize timing properties of latches to achieve timing closure in an efficient way. It also discusses the pre-requisites for using latches in a timing path.

• Physical aware timing ECOs - Challenges and Solutions
• The importance of being location aware while finding timing ECOs is discussed in this paper and guides the timing engineer about the same.

• I/O interfaces - An STA perspective
• The SoC interactions have been discussed with an angle of timing in this paper.

• Post-CTS clock path timing and automation in physical design flow
• This paper discusses, from various angles, various innovative techniques of automation that can be employed in physical design flow.

• Pre-CTS clock path timing and automation in physical design flow
• This paper discusses various innovative techniques of automation and scripting techniques that can be employed in physical design flow.

• Modelling skew requirements for interfacing signals in an SoC
• There are various protocols involved in modern day SoCs that enable communication accross SoCs. The modeling of timing requirements of these protocol signals is discussed in this paper.

• Timing challenges for SoC integration of ADC
• This paper discusses various timing and other backend challenges involved while integrating ADC or any other analog/hard macro into SoC.

• Using multi-bit flops to achieve better SoC design efficiency
• Usage of custom cells (other than basic logic gates) such as multi-bit flops to achieve optimum design efficiency is the prime focus of this paper.

• Low power, high density clock gate
• This paper discusses an approach to a power and area efficient design through a low power clock gating scheme for clock power improvement that reduces power dissipation by deactivating the clock signal to an inactive value (for clock gating cell) when clock is supposed to be gated (for Soc).